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| [AKD4368-B] AKD4368-B AK4368 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4368 is an evaluation board for 24bit DAC with integrated Headphone Amplifier, AK4368. The AKD4368 has the interface with AKM's ADC evaluation boards. Therefore, it's easy to evaluate the AK4368. The AKD4368 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4368-B --Evaluation board for AK4368 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.) FUNCTION * Compatible with 2 types of interface - Direct interface with AKM's A/D converter evaluation boards - On-board AK4116 as DIR which accepts optical input * 10pin header for serial control interface * Mini-jack for external Stereo Speaker * On-board Class-D Speaker Amplifier (AK7830) Vcc(5.0V) GND Regulator 3.3V Opt In (PORT1) DSP 10pin Header (PORT2) AK4116 (DIR) HPL HPR HP AK4368 AK7830 (SPK-Amp) SPPL SPPR Control Data 10pin Header (PORT3) L/RIN MIN ROUT LOUT L/ROUT Figure 1. AKD4368 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. 2007/08 [AKD4368-B] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. [VCC] (red) = 5.0V : for SPK-Amp (typ. 5.0V) [AGND] (black) = 0V : for analog ground [DGND] (black) = 0V : for logic ground Each supply line should be distributed from the power supply unit. 3.3V is supplied to AK4368 and AK4116 via the regulator. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4368 and AK4116 should be resets once bringing SW1(DAC/DIR_PDN) "L" upon power-up. And the AK7830 should be resets once bringing SW2(SPK_PDN) "L" upon power-up. Evaluation mode When evaluating the AK4368 using the PORT1(AK4116), it is possible to use the initial setting of the audio interface format (24bit MSB justified). When inputting the data from the PORT2, the AK4368's audio interface format should be set to correspond the input data's audio interface format. Refer to the AK4368's datasheet. Applicable Evaluation Mode (1) PLL Master Mode (2) PLL Slave Mode (3) EXT Slave Mode (3-1) In case of using DIR (Optical Link) (1) PLL Master Mode PORT2(DSP) is used. Nothing should be connected to PORT1(DIR). BICK and LRCK are supplied from PORT2. It is possible to evaluate at various sampling frequencies using built-in the AK4368's PLL. 27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz AK4368 MCKI MCKO BICK LRCK SDATA DSP or P 256fs/128fs/64fs/32fs 32fs, 64fs 1fs MCLK BCLK LRCK SDTO Figure 2. PLL Master Mode JP3(MCLK),JP4(BICK),JP5(LRCK) and JP6(SDTO) should be open. JP8(LRCK2) and JP9(BICK2) should also be open. The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of 2007/08 [AKD4368-B] DSP. The JP8(LRCK2) and JP9(BICK2)'s right side should be connected to LRCK and BICK of DSP. In case of supplying MCKO to DSP, the test pin(MCKO) should be connected to MCLK of DSP. JP3 MCLK JP4 BICK JP5 LRCK JP6 SDTO JP8 LRCK2 JP9 BICK2 (2) PLL Slave Mode PORT2 (DSP) is used. MCLK,BICK,LRCK and SDATA are supplied from PORT2. The test pin(MCKO) should be connected to MCLK of DSP. Nothing should be connected to PORT1 (DIR). MCKO is needed for a synchronous singal of BICK and LRCK. 27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz AK4368 MCKI MCKO BICK LRCK SDATA DSP or P 256fs/128fs/64fs/32fs 32fs, 64fs 1fs MCLK BCLK LRCK SDTO Figure 3. PLL Slave Mode JP8(LRCK2) and JP9(BICK2) should be short. JP3(MCLK),JP4(BICK),JP5(LRCK) and JP6(SDTO) should be open. JP3 MCLK JP4 BICK JP5 LRCK JP6 SDTO JP8 LRCK2 JP9 BICK2 2007/08 [AKD4368-B] (3) EXT Slave Mode AK4368 MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDATA 32fs 1fs MCLK BCLK LRCK SDTO DSP or P Figure 4. EXT Slave Mode (3-1) In case of using DIR (Optical Link) PORT1 (DIR) is used. DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector (TORX141). Nothing should be connected to PORT2(DSP). JP3(MCLK),JP4(BICK),JP5(LRCK) and JP6(SDTO) should be shorted. JP8(LRCK2) and JP9(BICK2) should also be short. JP3 MCLK JP4 BICK JP5 LRCK JP6 SDTO JP8 LRCK2 JP9 BICK2 The AK4116 operates at fs of 32kHz or more. If the fs is slower than 32kHz, any other evaluation mode without using DIR should be used. (3-2) In case of connecting AK4368 with external DSP PORT2 (DSP) is used. MCLK, BICK, LRCK and SDATA are supplied from PORT2. Nothing should be connected to PORT1 (DIR). JP3(MCLK),JP4(BICK),JP5(LRCK) and JP6(SDTO) should be open. JP8(LRCK2) and JP9(BICK2) should be short. JP3 MCLK JP4 BICK JP5 LRCK JP6 SDTO JP8 LRCK2 JP9 BICK2 Other jumper pins set up JP1 (GND) : Analog ground and Digital ground OPEN : Separated. 2006/02 [AKD4368-B] The function of the toggle SW Upper-side is "H" and lower-side is "L". [SW1] (DAC/DIR_PDN): Power down of AK4368 and AK4116. Keep "H" during normal operation. [SW2] (SPK_PDN): Power down of AK7830. Keep "H" during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4116. LED turns on when some error has occurred to AK4116. 2006/02 [AKD4368-B] Serial Control The AK4368 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (uP -IF) with PC by 10 wire flat cable packed with the AKD4368. Connect PC CSN CCLK CDTI AKD4368 10 Wire Flat Cable 10pin Connector 10pin Header Figure 5. Connect of 10 wire flat cable (1) 3-wire Serial Control Mode The jumper pins should be set to the followings. JP7 CAD0 JP2 I2C_SEL JP10 SDA I2C 3-wire (2) I2C-bus Control Mode The jumper pins should be set to the followings. (2-1) In case of using CAD0=0 (device address bits). JP7 CAD0 JP2 I2C_SEL JP10 SDA I2C 3-wire (2-2) In case of using CAD0=1 (device address bits). JP7 CAD0 JP2 I2C_SEL JP10 SDA I2C 3-wire 2006/02 [AKD4368-B] Input / Output circuit & Set-up jumper pin for Input / Output circuits (1) Input Circuit LIN, RIN and MIN Input circuits C15 1u RIN J1 LIN/RIN 6 4 3 C16 1u LIN J2 MIN 6 4 3 C17 1u MIN Figure 6. MIN, LIN, RIN Input circuits (2) Output Circuit 1) HPL, HPR Output Circuit C18 100u C19 100u R9 (SHORT) R10 (SHORT) 6 4 3 J3 HP HPR HPL Figure 7. HPL,HPR Output Circuit 2) LOUT, ROUT Output Circuit C20 1u R11 47k C21 1u R13 47k R14 220 6 4 3 R12 220 J4 LROUT ROUT LOUT Figure 8. LOUT, ROUT Output Circuit 2006/02 [AKD4368-B] 3) SPEAKER Output Circuit VC L P VC_L_P VC_L_N VC_L_N 6 4 3 J5 SPP L VC R P VC_R_P VC_R_N VC_R_N 6 4 3 J6 SPP R Figure 9. SPK-Amp Output Circuit AKM assumes no responsibility for the trouble when using the above circuit examples. 2006/02 [AKD4368-B] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4368 according to previous term. 2. Connect IBM-AT compatible PC with AKD4368 by 10-line type flat cable (packed with AKD4368). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4368 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "akd4368.exe" to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button Explanation of each buttons 1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK4368. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet. Explanation of each dialog [AKD4368-B] 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4368, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4368, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate DATT There are dialogs corresponding to register of 05h,06h and 09h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4368 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4368, click [OK] button. If not, click [Cancel] button. 2006/02 [AKD4368-B] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4368. The file type is the same as [SAVE]. 2006/02 [AKD4368-B] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The default setting sequence DAC->HP(3D=OFF) is displayed. Jump to (3) below if the default setting sequence is used. Go to (2) if the other setting sequence is required. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks". Figure 10. Window of [F3] 2006/02 [AKD4368-B] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 10 opens. Figure 11. [F4] window 2006/02 [AKD4368-B] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 11. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks") Figure 12. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. 2006/02 [AKD4368-B] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 12 opens. Figure 13. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 14. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed. 2006/02 [AKD4368-B] Figure 14. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. 2006/02 [AKD4368-B] MEASUREMENT RESULTS [Measurement condition] * Measurement unit : Audio Precession System Two Cascade * MCLK : 11.2896MHz * BICK : 64fs * fs : 44.1kHz * Bit : 24bit * Measurement mode : EXT Slave mode * Power Supply : VDD = 5.0V(AVDD = HVDD = DVDD = PVDD = 3.3V) * Measurement Filter : 22Hz 20kHz * Temperature : Room Parameter DAC Analog Output Characteristics DAC -> HPAMP THD+N (-3dBFS Output) D-Range (-60dB Output, A-weighted) S/N (A-weighted) DAC -> LOUT THD+N (0dBFS Output) D-Range (-60dB Output, A-weighted) S/N (A-weighted) Result (Lch / Rch) -57.6 / -57.7 92.6 / 92.7 92.9 / 93.1 -62.4 / -61.6 90.5 / 90.0 90.7 / 90.3 Unit dB dB dB dB dB dB 2006/02 [AKD4368-B] [Plot of Headphone Amp] AKM +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 AK4368 HP-AMP THD+N vs. Input Level (fs=44.1kHz, fin=1kHz) -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0 Figure 15. THD+N vs. Input Level AKM -20 -25 -30 -35 -40 -45 -50 d B r A -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 20 50 AK4368 HP-AMP THD+N vs. Input Frequency (fs=44.1kHz, fin=-3dB) 100 200 500 Hz 1k 2k 5k 10k 20k Figure 16. THD+N vs. Input Frequency 2006/02 [AKD4368-B] AKM +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 AK4368 HP-AMP Linearity (fs=44.1kHz, fin=1kHz) -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0 Figure 17. Linearity AKM -0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 20 AK4368 HP-AMP Freq Response (fs=44.1kHz, fin=-3dB) d B r A 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 18. Frequency Response (Boost off) (including external HPF) 2007/08 [AKD4368-B] AKM +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 AK4368 HP-AMP FFT (fs=44.1kHz, fin=-3dB) 200 500 Hz 1k 2k 5k 10k 20k Figure 19. FFT Plot(1kHz,-3dB) AKM +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 AK4368 HP-AMP FFT (fs=44.1kHz, fin=-60dB) 200 500 Hz 1k 2k 5k 10k 20k Figure 20. FFT Plot(1kHz,-3dB) 2007/08 [AKD4368-B] AKM +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 AK4368 HP-AMP FFT (Noise Floor) 200 500 Hz 1k 2k 5k 10k 20k Figure 21. FFT Plot(Noise Floor) AKM +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 AK4368 HP-AMP FFT Out-band Noise 500 1k Hz 2k 5k 10k 20k 50k 100k Figure 22. Out-band Noise 2007/08 [AKD4368-B] AKM +0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 20 AK4368 HP-AMP Crosstalk (fs=44.1kHz, fin=-3dB) 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 23. Crosstalk 2007/08 [AKD4368-B] REVISION HISTORY Date (yy/mm/dd) 05/10/31 06/02/10 07/08/01 Manual Revision KM081300 KM081301 KM081302 Board Revision 0 1 Reason First Edition Change Circuit Change Page Contents 2 24 The connection between GND and the pin3 of Mini-jack J5 and J6 were cut. C12 4.7nF 47nF IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. 2007/08 A B C D E RIN E HPL MIN LIN DGND JP1 GND AGND E C14 10u + R6 10k C12 47n B2 A4 B3 B4 A6 B5 A3 A5 A7 C3 D U1 D A2 C13 0.1u PVSS VCOC HPL MIN RIN LIN NC NC PVDD NC NC HPR A1 NC B7 HPR TP1 MCKO 1 B1 MCKO HVSS B6 C2 AVDD_REG JP2 I2C_SEL MCKI R8 47k 10 R1 51 D1 MCKI MUTET D6 D2 C I2C AVDD D7 R2 BICK R3 LRCK R4 CDTI R5 SDATA 51 E1 BICK VCOM E7 51 E2 LRCK NC G7 C5 0.1u 51 F1 SDA/CDTI CAD0/CSN SCL/CCLK ROUT E6 3DCAP1 3DCAP2 F2 3DCAP3 51 SDATA NC PDN LOUT F7 NC NC G1 G2 F3 G3 F4 G4 F5 NC G5 F6 C3 4.7n C4 B G6 470n CCLK A CSN PDN A B C + + AK4368 + + + R7 C1 10u C2 0.1u C1 DVDD HVDD C7 C9 1u C8 10u AVDD_REG C C7 0.1u + C6 2.2u + DVSS AVSS C6 C10 0.1u C11 10u HVDD_REG ROUT LOUT B A Title Size AKD4368-B Rev.1 Document Number A3 Date: D AK4368 Sheet E Rev A 1 of Wednesday, August 01, 2007 6 A B C D E E E J1 LIN/RIN 6 4 3 RIN C16 1u + LIN HPR 6 + C15 1u C18 100u R9 (short) J3 HPL + + C19 100u R10(short) 4 3 HP J2 MIN 6 4 3 C17 1u MIN ROUT R11 47k J4 6 D D + C20 1u R12 220 LOUT R13 47k + 1 + C21 1u R14 220 4 3 LROUT TP5 VC_L_P VC_L_P 6 J5 4 3 C TP6 VC_L_N C VC_L_N 1 SPP_L TP3 VC_R_P VC_R_P 1 6 J6 4 3 TP4 VC_R_N VC_R_N 1 SPP_R B B A A Title Size AKD4368-B Rev.1 Document Number A3 Date: A B C D Input/Output Sheet E Rev A 2 of Friday, February 10, 2006 6 A B C D E D_REG 2 D_REG R19 10k U3C 74HC14 5 14 6 7 D_REG U4 U3D 74HC14 9 14 8 7 E D1 1S1588 E PDN PDN1 SDATA 1 11 Y8 A8 9 PDN1 12 L 3 H 1 Y7 A7 8 SDTO1 SW1 DAC/DIR_PDN 2 C35 0.1u JP8 LRCK2 LRCK JP9 BICK2 BICK 14 Y5 A5 6 13 Y6 A6 7 LRCK1 BICK1 MCKI 15 Y4 A4 5 MCLK1 D_REG D D_REG 2 D_REG U3F 74HC14 14 10 7 13 14 12 7 CSN 16 Y3 A3 4 CSN1 D D2 1S1588 R20 10k U3E 74HC14 11 CCLK JP10 SDA SPK_PDN CDTI 3-wire I2C 17 Y2 A2 3 CCLK1 1 18 Y1 A1 2 CDTI1 L 3 1 H 10 SW2 SPK_PDN 2 C36 0.1u D_REG C37 0.1u 20 GND G2 19 VCC G1 1 74LVC541 C C JP3 DIR_MCLK MCLK JP4 DIR_BICK BICK B MCLK1 D_REG R22 R24 R26 10k 10k 10k R23 R25 R27 470 470 470 CSN1 CCLK1 CDTI1 BICK1 JP5 DIR_LRCK LRCK JP6 DIR_SDTO SDTO LRCK1 1 2 3 4 5 PORT3 10 9 8 7 6 B CSN SCL/CCLK SDA/CDTI CDTO SDTO1 CDTO JP7 CAD0 uP-I/F PORT2 MCLK BICK LRCK SDTI D_REG U3B 74HC14 3 14 4 7 1 2 3 4 5 10 9 8 7 6 GND GND DSP A D_REG R21 10k Title Size A AKD4368-B Rev.1 Document Number A3 Date: A B C D CLOCK Sheet E Rev A 3 of Friday, February 10, 2006 6 A B C D E D_REG E C26 0.1u C27 0.1u 1 VCC +5V L5 47u PDN L4 10u 1 1 2 D_REG DIR_REG HVDD_REG AVDD_REG L3 (short) 2 E PORT1 VCC GND OUT 3 2 1 TORX141 R15 470 C34 10u DIR_REG C33 0.1u + IN + C22 47u GND C28 0.1u T1 TA48M33F SPK_REG C23 0.1u OUT L2 (short) 1 1 2 2 L1 (short) 2 C24 0.1u + C25 47u D_REG U3A 74HC14 1 14 2 7 D R18 12k D R17 1k 2 LED1 ERF 1 D_REG 19 18 20 U2 AVSS 17 1 AVDD INT0 R PDN 16 RX0 INT1 15 R16 5.1 DIR_REG + 10u C30 C31 10p C32 10p C29 0.1u TP2 XTI X1 11.2896MHz 2 5 XTO CDTO 11 2 DVDD CSN 14 CSN 3 DVSS AK4116 CCLK 13 CCLK C C 11 4 XTI CDTI 12 CDTI CDTO 6 7 8 9 B 10 MCKO DAUX SDTO LRCK BICK B DIR_BICK DIR_SDTO A DIR_MCLK DIR_LRCK A Title Size AKD4368-B Rev.1 Document Number A3 Date: A B C D DIR Sheet E Rev A 4 of Friday, February 10, 2006 6 A B C D E E E D SPK_REG C43 10u C42 0.1u VC_R_P U5 VC_R_P VSS2 VSS1 VDD2 VDD1 VSS3 D VC_R_N VC_R_N VCOIL VC_L_P VC_L_P TEST VC_L_N C VC_L_N AK7830 BST_PD_N C VSS4 VFB C41 0.1u SPK_REG VBAT DVDDI D_REG IN_R_N IN_R_P IN_L_N IN_L_P PD_N SDA SCL VC SPK_PDN C38 0.1u LOUT C39 0.1u B AK7830 C40 0.01u B ROUT A A Title Size AKD4638-B Rev.1 Document Number A3 Date: A B C D SPK AMP Sheet E Rev A of Friday, February 10, 2006 6 6 |
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